(공고문-재안내) 2024년 반도체 글로벌 첨단팹 연계 활용사업(인턴쉽 및 기술인력교류) imec 인턴십 파견자 선정공고.hwp
닫기(과기정통부 지원) 2024년도 반도체 글로벌 첨단 팹 연계활용사업
해외(imec) 인턴십 파견자 선정공고 안내
과기정통부에서 시행하는 2024년도 반도체 글로벌 첨단팹 연계활용사업- 인턴십 및 기술인력교류 프로그램(해외 에 참여할 인턴십 파견자 선정계획을 아래와 같이 안내 하오니 이공계 대학원생(석·박사 과정)의 많은 관심과 참여 부탁드립니다.
2024.10.28.
<주무부처> 과학기술정보통신부 원천기술과
<전문기관> 한국연구재단 반도체‧디스플레이단
<주관연구기관> 나노종합기술원 대외협력실
1. 사업개요 |
□ 사업목적
ㅇ 해외 반도체 첨단인프라 기반의 주요 연구거점 기관과의 공동프로젝트 수행 및 인턴십 활동을 통한 미래 첨단 반도체 분야 글로벌 기술 협력 소양을 갖춘 전문 R&D 인재양성
□ 사업 내용
ㅇ 반도체 분야 해외 유수 R&D기관인 벨기에 imec*에서 추진하는 공동연구프로젝트 참여 수행을 위한 현지 연수 지원(형태: 인턴십)
* (imec) 나노전자 및 디지털테크분야에서 300mm 반도체 파일럿 라인과 600개 이상 글로벌 기업, 96개국 5,500명의 전문인력이 참여하는 세계 최고 수준의 연구 역량을 보유한 최대 인프라· R&D 기관
□ 공동연구개발 프로젝트 참여 분야
ㅇ 반도체 설계/공정, 메모리/시스템 반도체, 나노바이오, 첨단패키징 등
ㅇ imec 내부 연구책임자 제안 연수주제(12개) 리스트 참조
* 연수주제 별 수행사항은 붙임(imec 연수주제별 운영 계획) 참고
2. 지원대상 및 자격요건 |
□ 지원 대상
ㅇ (국적) 대학민국 국적 소지자(남성은 병역 관련 법령에 따른 해외체류 가능한자)
ㅇ (학력) 국내 대학원 석사, 박사 재학생(통합과정 포함)
* 한국 내 대학, 연구원 등에서 학위 과정 중이어야 하며, 학부생, 졸업생 및 유학생은 지원 불가
ㅇ (전공) 연수 분야 관련 이공계 전공 국내 석·박사 재학생
* 융복합 또는 자유전공인 경우 주요 이수 과목을 이공계열로 볼 여지가 있는 경우 지원 가능
ㅇ 최종 선발된 이후 연수 가능한 자(2025년 1월)
ㅇ (지원 제한 대상) 최근 3년간 유사 사업(연구개발사업 포함) 참여 또는 해외기관에 파견된 자
□ 지원 자격(어학·성적)
(재안내) 공인 어학성적을 보유하고 있지 않은 대학원생 지원자 중 해외 연수기관(imec) 연구자와 사전협의 과정에서 영어 면제 추천서(연구활동 가능수준 등)를 받는 경우 어학점수 대체 가능 |
ㅇ (성적) 최종학위 성적 3.37/4.5 이상 우수자
* 학점 변환기준: 3.0/4.0, 3.22/4.3, 3.75/5.0, 75/100 이상으로, 석박사통합과정 재학생은 최근 2개년 이상 성적을 최종학위 성적으로 인정 가능
* 석박사통합과정 재학생은 최근 2개년 이상 성적을 최종학위 성적으로 인정 가능
* 석사과정 1학기 미만인자는 학부 성적으로 대체 가능
ㅇ (어학) 영어 토익 770점, 토플 IBT 88점, 토익스피킹 IM3(130점), IELT 6.5점, TEPS 613점, TEPS-S 55점, New-TEPS 294, OPIC IM2
* 어학성적은 지원접수 마감일 기준 유효기간이 만료되지 않은 국내 정기시험 성적에 한하여 인정하며 조회 불가 성적은 불인정(단, 사이버국가고시센터에 등록된 어학성적의 경우 5년까지 인정)
□ 지원내용 및 기간
ㅇ (지원사항) 해외 연구기관에서 공동연구를 수행할 수 있는 출입국 비용(왕복항공료, 의료보험료, 비자수수료) 및 체재비(인건비 포함) 지원
구분 |
석사(12개월 기준) |
박사(12개월 기준) |
지원내역(안) |
약 40백만원 |
약 55백만원 |
* 정부 지원금 이중수혜는 불가(정부지원 과제 참여 등), 협약 체결일 환율을 기준으로 산정 지원
* 비자 발급, 숙소, 등록 등은 파견자 선정 이후 imec 등과 협의하여 파견준비 진행 절차 등 안내 예정
ㅇ (지원규모) 16명 내외(연수기간, 예산 등에 따라 조정될 수 있음)
ㅇ (연수기간) 12개월(예정 2025. 1. ~ 2025. 12.) 이내
* 파견 연수 시점은 연수대상자 및 연구기관 공동연구책임자와 협의 후 최종 확정
3. 사업신청 및 제출서류 |
□ 신청기간 ※ 상기 일정은 추진 상황에 따라 변동될 수 있음
ㅇ (공고 및 신청) 2024년 10월 28일(월) ~ 11월 15일(금) 18:00까지
ㅇ 추진일정
구분 |
주체 |
추진내용 |
2024∼2025년 |
||
사업 공고 (연수생 모집) |
한국연구재단 나노종합기술원 |
연수생 선발 모집 통합 공고 |
10월 말 |
||
연수생 자격요건 사전검토 |
나노종합기술원 |
연수생 서류 제출 → 나노종합기술원 사전검토 |
11월 |
||
선정평가 및 최종선정 |
선정평가위원회 |
연수생 선정평가 실시 및 최종 선정심의(대면 등) |
11월 |
||
연수생 출국 준비 |
나노종합기술원, 연수생, imec |
연수생 최종 확정 및 출국준비(협약체결 포함) |
12월~1월 |
||
연수생 출국 |
연수생 |
imec 연수 참여 |
2025년 1월 |
□ 신청방법 및 절차
ㅇ 신청방법: 접수 기한 내 주관연구기관 메일주소 ()로 신청서를 포함한 필수 서류 제출
ㅇ (연수주제 사전협의) 사업 참여신청 前 imec 연구책임자와 메일/유선 (인터뷰) 등을 통해 연구 수행 가능성(연수주제, 기간 등) 확인, 이후 지원 (imec 책임자와의 협의결과 지원 가능 확인할 수 있는 메일, 확인서 필첨)
□ 연수주제(안)
ㅇ (희망 연수주제 선정) imec 연구원 제시 주제 확인 후 imec 연구책임자와 사전협의
구분 |
연수주제 |
연구책임자 |
1 |
Development of tip array sensors for characterization of nanoelectronics device structures by SPM |
Thomas Hantschel |
2 |
Development of advanced SPM tomography for characterization of nanoelectronics device structures |
Thomas Hantschel |
3 |
High stability mechanism of CQD photodiodes for SWIR detection |
Sangyeon Lee |
4 |
Study of high aspect ratio gate etch for advanced CMOS transistor technologies |
Emmanuel DUPUY |
5 |
Infrared Depth sensing with Colloidal Quantum Dot Photodetectors |
Joo Hyoung Kim |
6 |
Advanced plasma etching of novel materials |
Leila Ghorbani |
7 |
Artifact-tolerant analog frontend for neuromodulation system in high-voltage BCD technology |
Chutham |
8 |
Corrective selective hard mask growth for High NA patterning |
Rémi Vallat |
9 |
Study of dep/etch cycling process for high aspect ratio etch |
Subhobroto Choudhury |
10 |
Development of plasma dicing process for 3D integration |
Violeta Georgieva |
11 |
Wet processing of high aspect ratio nanostructures |
Guy Vereecke |
12 |
In-situ ATR-FTIR study of wetting transition on HAR nanostructures |
Xiumei Xu |
□ 제출서류
구분 |
제출서류 |
주요 내용 |
구분 |
파일 형태 |
1 |
신청서 |
서식1호 |
필수 |
hwp |
2 |
국·영문 이력서 |
자유 서식 |
필수 |
|
3 |
국·영문 연수 수행계획서 |
서식2호 |
필수 |
hwp |
4 |
지도교수 추천서 |
서식3호 |
필수 |
|
5 |
imec 사전 협의 내용 |
이메일, 확인서 등 내용(증빙)을 통해 인턴십 참여가능(주제, 기간, 자격 등) 확인 |
필수 |
메일 증빙 |
6 |
재학증명서 |
(석사/박사) 재학증명서 |
필수 |
|
7 |
성적증명서 |
(석사/박사) 성적증명서 |
필수 |
|
8 |
공익어학성적증명서 |
어학 기준 참고 |
필수 |
|
9 |
서약서 |
서식4호 |
필수 |
|
10 |
개인정보이용동의서 |
서식5호 |
필수 |
|
4. 선정평가 |
□ 평가 기본방향
ㅇ 주관기관은 연수자 선정위원회의 객관성·공정성 확보를 위해 지원자 제출 서류 사전검토 (imec 사전협의 내용, 어학, 성적)를 추진하며 결격사유가 없는 지원자에 대한 발표평가를 위한 선정위원회(내·외부 전문가 7인 내외) 구성
ㅇ 평가점수가 70점 이상인자는 선정대상이 되며 선정대상이 선정하고자 하는 규모보다 많을 경우 평가점수가 높은 순으로 선정함
□ 평가방법 : 발표평가 (연수생 발표 및 질의응답)
※ 평가대상 규모, 연수주제 등에 따라 분야별, 주제별 평가위원회 구성 가능
□ 선정절차
①사전검토 |
② 선정평가 |
③최종 선정 |
④선정공고 |
|||
응모자격 및 제출 서류의 적절성 검토 (I imec 사전협의 결과 등) |
➡ |
위원별 개별평가 (과제별 평가점수 부여) |
➡ |
연수대상자 최종 선정 (예비선정 후보자 포함) |
➡ |
평가결과 공고 (개별, 홈페이지등) |
나노종합기술원 |
선정위원회 |
나노종합기술원 |
나노종합기술원 |
ㅇ (사전검토) imec 연구책임자와 사전협의(연구주제, 일정 등)메일 내용 확인을 통한 공동연구/파견 가능 여부 및 신청 자격(어학, 성적) 확인
ㅇ (발표평가) 연수생이 제출한 연구개발계획서 내용을 토대로 발표 및 평가위원 질의·응답 등을 통해 평가 실시
□ 평가항목
구분 |
평가 내용 |
배점 |
필요성 |
·연구(연수)의 필요성 및 계획 구체성 |
30 |
수행능력 |
·연구계획의 창의성 ·연구계획의 충실성 ·연구수행 역량 ·유사연구 수행 경험 등 |
40 |
발전 가능성 및 기대성과 |
·연구(연수)성과 활용 계획의 타당성 ·연구 수행 이후 향후 기대효과 |
30 |
합 계 |
※ 최종 평가점수는 평가위원이 부여한 점수 중에 최고점과 최저점을 1개씩 제외한 점수의 산술평균값으로 도출(소수점 셋째 자리에서 반올림)
※ 평가점수가 동점일 경우, 배점의 평가항목 평가점수가 높은 순으로 우선순위 부여
5. 사업 신청시 유의사항 |
□ 사업신청 시 유의사항
ㅇ 마감일 이후 신청서 제출, 제출 서류 미비, 타 과제와의 연구 내용 중복, 신청자격 부적격 등의 경우에 평가에서 제외 가능
ㅇ 각종 증빙자료의 기산일은 공고일 기준임(단, 참여 제한의 경우 신청마감일 전일을 기준으로 함)
ㅇ 제출된 서류는 선정평가 등 사업 운영을 위해 연수기관 및 평가위원에게 제공될 수 있으며, 평가 결과의 세부 내용은 공개하지 않음
ㅇ 사실과 다른 내용을 연구계획서, 별첨자료 등에 기재한 경우 제재(선정 취소 등) 가능
□ 파견 연수생 의무사항
ㅇ 출입국 등에 필요한 기간을 제외한 실제 연수기간을 기준으로 해외 체류기간(12개월 이내)을 준수해야 함
ㅇ 동 사업을 지원받은 연수대상자는 해외 연구·연수 종료 후 14일 이내 반드시 귀국하여야 함(개인적인 사유로 체류에 따른 항공편 변경 등 관련 비용 지원 불가) 불가항력적인 경우가 아님에도 14일 이내 귀국 의무를 준수하지 않을 경우, 해당자에 지원된 국비 전액을 주관기관에 반납하고, 주관기관은 해당 금액을 정산시 전문기관에 반납함
ㅇ 동 사업을 지원받은 연수대상자가 불가항력적인 경우가 아님에도 공동연구 수행을 중단하거나 의무사항을 불이행·불성실하게 수행하는 경우, 해외 연구(연수)기관으로부터 연수 중단 통보를 받은 경우, 또는 제출기한 내에 연구수행 결과물 미제출시, 해당자에 지원된 국비 전액 이내를 주관기관에 반납하고, 주관기관은 해당 금액을 정산 시 전문기관에 반납함
ㅇ 연수기간 중 국내 체류 가능일은 해외 체류 1개월 기준 1일을 허용하며, 개인별 국내 체류 가능일을 초과하는 경우 체재비를 일할 계산하여 반납해야 함(연수 기간에 대한 출입국사실을 위한 증명서는 결과보고서 내 별첨 제출)
ㅇ 연수기간 동안 연수생은 출석, 지적재산/기밀유지, 안전, imec 정책 준수 등의 의무사항 준수
ㅇ 상기 내용 이외 사항은 관련지침 및 관계규정, imec 내부기준에 따름
□ 파견 연수생 결과물 제출(성과목표)
ㅇ (성과물) 파견기간 동안의 성과물은 imec 연구원과 인턴십 파견자간의 협의를 통해 결정(imec은 성과도출에 필요한 기회, 환경 및 기술적 지원 제공)
- imec 내부 성과발표회 발표 또는 저널/학회 논문 게재
- (연수 6개월) imec 내부(mini) 컨퍼런스 구두발표회 개최(imec 책임자, 파견자, NNFC 등)를 통한 중간점검, (연수 11개월) imec 최종 발표회(우수결과에 대해 저널 논문기고 기회 부여), (연수 12개월) 발표회 결과 반영 최종 성과보고서 작성 지원 등
ㅇ (착수보고서) 연수 개시일로부터 1개월 이내 주관기관으로 제출
* 연수기관 도착 이후 1주일 이내 현지 도착보고 진행(현안 발생시 수시)
ㅇ (중간보고서) 연수 개시 6개월 경과 시점에서 주관기관으로 제출
ㅇ (결과보고서) 연수 종료 후 1개월 이내 주관기관으로 제출(출입국사실증명서 필수)하고, 귀국 후 연수결과 발표회 참여
ㅇ (연구노트) 매월 연구노트 작성 및 제출(파견자, 책임자 확인)
* imec 연구책임자와 소통을 통해 지속 연수 진행 유무 판단, 양식 등은 imec 협의 이후 제공
□ 파견 연수 지원금 지급방식
ㅇ (직접지급) 주관기관 → 연수생 계좌(본인명의 계좌) 지급
ㅇ (체재비) 주관기관에서 연수생에게 직접 지급하며, 매월 연구노트 등 연수활동 확인후 지급
ㅇ (교통비) 항공료, 의료보험, 기타 수수료 등은 실비 지원
6. 사업문의 |
소속기관 |
부서 |
성명 |
전화번호 |
이메일 |
나노종합기술원 |
대외협력실장 |
남궁지 |
042-366-2040 |
ngjs@nnfc.re.kr |
대외협력실 |
조혜인 |
042-366-2063 |
chi0829@nnfc.re.kr |
붙임 |
IMEC 연수주제 별 운영 계획 |
□ Development of tip array sensors for characterization of nanoelectronics device structures by SPM
Department |
FAB/MCA |
Full Name of Mentor |
Thomas Hantschel |
|
Thomas.Hantschel@imec.be |
|
Project Period |
~01/06/24 - 31.05/25 (12 months) |
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Project Topic |
Development of tip array sensors for characterization of nanoelectronics device structures by SPM |
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Summary of Research project |
Development of advanced sensor structures for application in innovative scanning probe microscopy (SPM). Ultra-sharp tip structures will be fabricated and integrated into tip array chips. The student will design the lithography masks in the first phase. Then, the student will do the lithography, etching and coating steps in a cleanroom environment. The fabricated structures will be evaluated by inspection and SPM measurements |
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Monthly Plan |
1st Month |
Safety, cleanroom, lab & tool training, literature study |
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2nd Month |
Lithography mask design - version 1, literature study |
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3rd Month |
Cleanroom tip chip fabrication, diamond growth training |
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4th Month |
Cleanroom tip chip fabrication, diamond growth |
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5th Month |
Tip chip evaluation & measurements |
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6th Month |
Tip chip evaluation, mid-term presentation |
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7th Month |
Cleanroom tip chip fabrication, diamond growth training |
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8th Month |
Cleanroom tip chip fabrication, diamond growth |
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9th Month |
Tip chip evaluation & measurements |
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10th Month |
Tip chip evaluation & benchmarking |
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11th Month |
Finishing experiments, Drafting of results paper |
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12th Month |
Drafting of results paper, final results internship presentation in department meeting |
□ Development of advanced SPM tomography for characterization of nanoelectronics device structures
Department |
FAB/MCA |
Full Name of Mentor |
Thomas Hantschel |
|
Thomas.Hantschel@imec.be |
|
Project Period |
~01/06/24 - 31.05/25 (12 months) |
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Project Topic |
Development of advanced SPM tomography for characterization of nanoelectronics device structures |
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Summary of Research project |
Development of nanoelectrical device tomography based on innovative scanning probe microscopy (SPM) approaches whereby the material is nanomechanically removed in nanometer thick slices while being electrically probed in between slicing. The project involves the setup, execution and analysis of suitable 3D scanning experiments and the tomography data reconstruction. The measurements serve in the first part the further improvement of the technique and in the second part to gain a better understanding of the investigated device structures. |
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Monthly Plan |
1st Month |
Safety, lab & tool training, literature study |
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2nd Month |
Tool practising & skill improvement, sample prep, literature study |
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3rd Month |
Nanomechanical materials removal study |
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4th Month |
Nanoelectrical 3D device measurements |
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5th Month |
Tomography data visualization & interpretation |
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6th Month |
Tomography data visualization & interpretation, mid-term presentation |
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7th Month |
Device measurements & data analysis study |
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8th Month |
Device measurements & data analysis study |
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9th Month |
Device measurements & data analysis study |
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10th Month |
Device measurements & data analysis study |
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11th Month |
Finishing experiments, Drafting of results paper |
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12th Month |
Drafting of results paper, final results internship presentation in department meeting |
□ High stability mechanism of CQD photodiodes for SWIR detection
Department |
Sensors and Actuators |
Full Name of Mentor |
Sangyeon Lee |
|
Sangyeon.Lee@imec.be |
|
Project Period |
01/04/2024 ~ 31/03/2025 (12 months) |
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Project Topic |
High stability mechanism of CQD photodiodes for SWIR detection |
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Summary of Research project |
Colloidal qunatum dot based photodiode are studying for the alternative SWIR photodiode, consiting of III-V and MCT materials, because of cost-effective and monolitic processes. In this project, internship students will be conducting on the study of reliabilty mechansim of CQD photodiodes under various environments for SWIR detection |
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Monthly Plan |
1st Month |
Equipment traning, review of related papers |
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2nd Month |
Equipment traning, review of related papers |
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3rd Month |
Equipment traning, review of related papers / Conducting experiments |
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4th Month |
Conducting experiments |
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5th Month |
Conducting experiments |
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6th Month |
Conducting experiments |
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7th Month |
Conducting experiments |
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8th Month |
Conducting experiments |
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9th Month |
Conducting experiments / Deriving data |
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10th Month |
Deriving data |
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11th Month |
Deriving data / Writing paper (Journal of Materials Chemistry C) |
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12th Month |
Writing paper (Journal of Materials Chemistry C) |
□ Study of high aspect ratio gate etch for advanced CMOS transistor technologies
Department |
IMECBE-STS-APPM-UPM-ECCP-ETCH-ETCHSCE |
Full Name of Mentor |
Emmanuel DUPUY |
|
Emmanuel.Dupuy@imec.be |
|
Project Period |
(12 months) |
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Project Topic |
Study of high aspect ratio gate etch for advanced CMOS transistor technologies |
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Summary of Research project |
This research project is devoted to the study of gate etch at nanometer-scaled dimensions by optimization of process parameters using state-of-the art techniques and plasma reactors. The main objective of this work is to explore the relation between gate etching profile and plasma conditions. Plasma conditions including advanced pulsing modes will be screened and tuned for optimal gate profiles. The gate profile will be studied using X-SEM, CDSEM, and TEM. The intern will work in a 300 mm cleanroom. Basic training on working regulations is mandatory as a starting. Technical training on plasma processing and relevant metrology will be arranged, so that the intern can work independently. |
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Monthly Plan |
1st Month |
Equipment training, Review of related papers |
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2nd Month |
Equipment training, Review of related papers |
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3rd Month |
Equipment training, Review of related papers |
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4th Month |
Conducting experiments |
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5th Month |
Conducting experiments |
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6th Month |
Conducting experiments |
|||||
7th Month |
Conducting experiments |
|||||
8th Month |
Conducting experiments |
|||||
9th Month |
Conducting experiments |
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10th Month |
Summary data and review |
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11th Month |
Summary data and review |
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12th Month |
Drafting a paper |
□ Infrared Depth sensing with Colloidal Quantum Dot Photodetectors
Department |
SAT |
Full Name of Mentor |
Joo Hyoung Kim |
|
Joo.Hyoung.Kim@imec.be |
|
Project Period |
(12 months) |
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Project Topic |
Infrared Depth sensing with Colloidal Quantum Dot Photodetectors |
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Summary of Research project |
Colloidal Quantum Dot (CQD) technology can revolutionize non-visible imaging which is not accessible with silicon technology. It can offer exceptional performance at low-cost enabled by wafer-level monolithic integration. Markets include robotics, automotive, AR/VR and consumer electronics. Potential use cases include advanced face identification, eye tracking, night vision, advanced driver assistance systems (ADAS), multispectral machine vision for medical and industrial markets. CQD technology has shown excellent performance in SWIR imaging and its process has been made compatible with semiconductor manufacturing in a complementary metal oxide-semiconductor (CMOS) fab, and potentially high detectivity and high speed, making it more interesting for sensing (e.g. 3D/depth). Development of CQD Photodetector (CQDPD) is ongoing within imec targeting a fast photoresponse time. One of the most interesting application case will be doing the depth sensing based on gated imaging from this high speed performance at SWIR wavelengths, where the low solar radiation background and less light absorption or scattering is expected to have higher signal to noise ratio, thus better depth resolution, and maximum detection range. |
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Monthly Plan |
1st Month |
Setting up Imager measurement enviroments (Software, hardware) |
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2nd Month |
Imager full characteriazation |
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3rd Month |
Imager full characteriazation |
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4th Month |
Depth sensing feasibility tests (visible) |
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5th Month |
Depth sensing feasibility tests (visible) |
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6th Month |
IR depth sensing feasibility tests |
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7th Month |
IR depth sensing feasibility tests |
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8th Month |
IR depth sensing and mapping |
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9th Month |
IR depth sensing and mapping |
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10th Month |
Paperwork |
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11th Month |
Paperwork |
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12th Month |
Paperwork |
□ Advanced plasma etching of novel materials
Department |
IMECBE-STS-APPM-UPM-ECCP-ETCH-ETCHNOMA |
Full Name of Mentor |
Leila Ghorbani |
|
Leila.Ghorbani@imec.be |
|
Project Period |
12 months |
|||||
Project Topic |
Advanced plasma etching of novel materials |
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Summary of Research project |
The student will work on patterning of novel material combinations, in this case quaternary element-based chalcogenides, which are being considered for use in advanced high-speed memory applications. The student will learn to work on the advanced etch tools in the clean room which are used for patterning memory devices. He/She will expose the chalcogenide material to different plasma chemistries and will try to understand the impact of these chemistries on the surface morphology, stochiometry or crystallography of the deposited chalcogenide. These are very crucial aspects to understand as any change in the chalcogenide during its patterning into memory devices can impact its elctrical performance. |
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Monthly Plan |
1st Month |
Introduction to imec, etch tool trainings and studying plasma etch fundamentals |
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2nd Month |
Literature review on plasma etching of chalcogenides, characterization techniques and work on presentation skills, get trained on characterization tools. Work closely with Mentor - Leila |
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3rd Month |
Get trained and practice coupon work and start small experiments in the cleanroom. |
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4th Month |
The following steps will be carried out and repeated to understand what is an optimized or BKM recipe for chalcogenides. Plan experiments with mentor. Expose samples to different plasma chemistry(etchant) and conditions Physical characterization-AFM, SEM, TEM- To see if the surface is damaged Chemical characterization-XPS,FTIR,EDS-to observe chemical changes in the sample and understand the chemical bonding between the plasma etchant and the chalcogenide during etching Discussion and analyzing of the learnings with mentor and planning new experiments Repeats steps 1 to 4 till a suitable etch chemistry and condition which doesn’t impact the material physically and chemically is achieved. |
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5th Month |
||||||
6th Month |
||||||
7th Month |
||||||
8th Month |
||||||
9th Month |
||||||
10th Month |
||||||
11th Month |
||||||
12th Month |
Start making the framework or story that will be used to contribute to a journal paper |
□ Artifact-tolerant analog frontend for neuromodulation system in high-voltage BCD technology
Department |
LST-CSH_Neural |
Full Name of Mentor |
Chutham |
|
Chutham.Sawigun@imec.be |
|
Project Period |
12 months suitable for a Ph.D. student |
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Project Topic |
Artifact-tolerant analog frontend for neuromodulation system in high-voltage BCD technology |
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Summary of Research project |
This project aims to achieve a neural amplifier for use in multichannel bidirectional neural interface systems. It needs to tolerate common-mode input voltage up to 10Vpp that comes from stimulation artifacts. At the same time, it must maintains its ability to amplify differential input signals with moderate gain (>50x) and good linearity (<1% THD). This amplifier will be developed further from imec IP to be ready to tape out (design, simulation and layout) in high-voltage BCD technology. |
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Monthly Plan |
1st Month |
Literature review |
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2nd Month |
Literature review |
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3rd Month |
Critical analysis of the imec IP (artifact-tolerant ac-coupled neural amplifier) |
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4th Month |
Further develop the neural to meet the required specifications |
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5th Month |
Further develop the neural to meet the required specifications |
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6th Month |
Circuit design in BDC technology |
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7th Month |
Circuit design in BDC technology |
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8th Month |
Circuit design in BDC technology |
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9th Month |
Chip layout |
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10th Month |
Chip layout |
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11th Month |
Working on verification plans (measurement procedures and pcb design). |
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12th Month |
Paper drafting |
□ Corrective selective hard mask growth for High NA patterning
Department |
IMECBE-STS-APPM-UPM-ECCP-ETCH-ETCHADP |
Full Name of Mentor |
Rémi Vallat |
|
Remi.Vallat@imec.be |
|
Project Period |
(12 months) |
|||||
Project Topic |
Corrective selective hard mask growth for High NA patterning |
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Summary of Research project |
Challenges introduced with High NA EUV lithography will be defectivity management with ultra-thin resists while using low EUV dose1. Reducing the density of bridges and breaks is thus a major point of focus for its introduction2. Ultra-thin resists, at low EUV dose, may come with high bridge/ break density (positive/ negative-tone resist, respectively). In the case of bridges, a descum step is traditionally introduced, which creates breaks instead (in ultra-thin resists) and further reduces the resist budget for underlayer patterning. Therefore, recovering breaks is a strategic capability for defect reduction. The goal of the post-doc is to study the inner workings of existing processes to enable similar processes in other applications. The method consists of patterning an underplayer of suitable thickness for ultra-thin resists, and run a PECVD deposition process onto this prevent the formation of breaks. The way, the hard-mask budget is increased to prevent the formation of breaks during transfer into the stack, even and especially while patterning from an ultra-thin underlayer. Additionally, this method offers a reduced environmental footprint compared to conventional one as no or much thinner UL can be used requiring no or less high global warning potential gases to be used. More specifically, you will: Study the thermo-mechanical properties of the deposited material. Develop post deposition processes to adapt the film properties and composition to the targeted application, Investigate mechanisms of different defect mitigation approaches (atomic clean, super cycle, etc.), Identify the nucleation mechanisms on ultrathin layer. |
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Monthly Plan |
1st Month |
General Imec trainings + Software trainings + Equipment trainings + Review of related papers |
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2nd Month |
Software trainings + Equipment trainings + Review of related papers |
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3rd Month |
Software trainings + Equipment trainings + Review of related papers |
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4th Month |
Conducting an Experiment |
|||||
5th Month |
Conducting an Experiment |
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6th Month |
Conducting an Experiment |
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7th Month |
Conducting an Experiment |
|||||
8th Month |
Conducting an Experiment |
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9th Month |
Deriving Results Data |
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10th Month |
Deriving Results Data |
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11th Month |
Drafting a paper (JVSTA) |
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12th Month |
Drafting a paper (JVSTA) |
□ Study of dep/etch cycling process for high aspect ratio etch
Department |
IMECBE-STS-APPM-UPM-ECCP-ETCH-ETCHSCE |
Full Name of Mentor |
Subhobroto Choudhury |
|
Subhobroto.Choudhury@imec.be |
|
Project Period |
(12 months) |
|||||
Project Topic |
Study of dep/etch cycling process for high aspect ratio etch |
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Summary of Research project |
The advacned CMOs device development facing high aspect ratio etch process at Front-End-Of-Line (FEOL) features will be one of the main challenges to target better device performance. One of the well-known challenges is mask selectivity improvement without clogging/under etch issue. In this project, we plan to focus on the development of dep/etch cycling approaches to mitigate future challenges in increased stack thickness. |
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Monthly Plan |
1st Month |
Equipment training, Review of related papers |
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2nd Month |
Equipment training, Review of related papers |
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3rd Month |
Equipment training, Review of related papers |
|||||
4th Month |
Conducting an Experiment |
|||||
5th Month |
Conducting an Experiment |
|||||
6th Month |
Conducting an Experiment |
|||||
7th Month |
Conducting an Experiment |
|||||
8th Month |
Conducting an Experiment |
|||||
9th Month |
Summary data and review |
|||||
10th Month |
Summary data and review |
|||||
11th Month |
Summary data and review |
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12th Month |
Drafting a paper |
□ Development of plasma dicing process for 3D integration
Department |
IMECBE-STS-APPM-UPM-ECCP-ETCH-ETCHSCE |
Full Name of Mentor |
Violeta Georgieva |
|
Violeta.Georgieva@imec.be |
|
Project Period |
(12 months) |
|||||
Project Topic |
Development of plasma dicing process for 3D integration |
|||||
Summary of Research project |
The 3D integration technology has received widespread attention from both academia and industry to create the desired breakthrough in chip scaling. Plasma dicing is a key interconnect technology for 3D integration in the future. It provides the opportunity to create vertically stacked chips in package, which can in turn deliver shorter interconnection delay, enable integration of heterogeneous technologies at a potentially lower cost and reduce time-to-market introduction. The Bosch process is widely used for plasma dicing to achieve vertical sidewalls in Si. The taper profile, bottom notching and side scallop-shaped roughness are well-known challenges for plasma dicing. The dielectric stack etch is however challenging and requires further improvement. Currently, it is done in the deep silicon etch chamber which has limitations considering dielectric etch. In this project, we plan to focus on the development of new process approaches to mitigate future challenges in increased thickness of the dielectric stack and possible separating the dielectric etch in a dedicated dielectric chamber. |
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Monthly Plan |
1st Month |
Equipment training, Review of related papers |
||||
2nd Month |
Equipment training, Review of related papers |
|||||
3rd Month |
Equipment training, Review of related papers |
|||||
4th Month |
Conducting an Experiment |
|||||
5th Month |
Conducting an Experiment |
|||||
6th Month |
Conducting an Experiment |
|||||
7th Month |
Conducting an Experiment |
|||||
8th Month |
Conducting an Experiment |
|||||
9th Month |
Summary data and review |
|||||
10th Month |
Summary data and review |
|||||
11th Month |
Summary data and review |
|||||
12th Month |
Drafting a paper |
□ Wet processing of high aspect ratio nanostructures
Department |
APPM |
Full Name of Mentor |
Guy Vereecke |
|
Guy.Vereecke@imec.be |
|
Project Period |
12 months |
|||||
Project Topic |
Wet processing of high aspect ratio nanostructures |
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Summary of Research project |
In semiconductor manufacturing, new generations of devices have entered the nano-world, with critical dimensions of the order of 10 nm. Moreover, new transistor geometries are vertical, with the generation of 1-D and 2-D nano-confined spaces. While many process steps are still performed using aqueous chemistries, e.g. wet etching of materials for patterning and wet cleaning of surfaces. Recent studies have shown that nano-confinement is affecting all the steps in a wet process from wetting to chemical reactions, rinsing and drying. Evidence was found for water structuring, decreased permittivity, modified chemical equilibria and slower diffusivity in nanoconfined solutions. Current activities target the wet etching of nanoconfined films, such as TiN in the RMG module of FinFET. In the etching tests, the etch rates on planar films are determined typically by ellipsometry, while cross-section-SEM (scanning electron microscopy) and image analysis are used on structures. Here the composition of etch chemistries are modified with additives to suppress the confinement effects. The student typically performs the wet etching tests, the ellipsometry measurements, the data treatment of the SEM pictures generated by operators in the pilot-line, and a kinetic analysis comparing planar to patterned etch rates, leading to new chemistry proposals. ATR-FTIR (attenuated total reflection Fourier-transform IR spectroscopy) can be used to confirm the impact of additives on water structuring, or to pre-select additives for testing. ATR- FTIR has become a major technique to characterize wetting and chemical reactions, as well as properties of aqueous solutions such as structuring, permittivity and diffusivity. Typically, the student prepares the ATR crystals (polishing), performs the FTIR tests using a home-build liquid cell, as well as the data treatment and interpretation. Progress in the understanding of phenomena are used to propose and test solutions to the confinement effects. The content of the student project will be adapted depending on the progress of our research. |
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Monthly Plan |
1st Month |
introduction to imec and trainings |
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2nd Month |
trainings |
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3rd Month |
experimental work |
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4th Month |
experimental work |
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5th Month |
experimental work |
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6th Month |
experimental work |
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7th Month |
experimental work |
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8th Month |
experimental work |
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9th Month |
experimental work |
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10th Month |
preparation of conference paper for UCPSS, ECS or SPCC, depending on timing) |
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11th Month |
presentation at conference, writing of journal paper |
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12th Month |
writing of journal paper and submission |
□ In-situ ATR-FTIR study of wetting transition on HAR nanostructures
Department |
UPM/ECCP |
Name of Mentor |
XiuMei Xu |
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XiuMei.Xu@imec.be |
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Project Period |
01/04/2024 ~ 31/03/2025 (12months) |
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Project Topic |
In-situ ATR-FTIR study of wetting transition on HAR nanostructures |
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Summary of Research project |
In-situ characterization techniques are critical for capturing the wetting transition on nanostructures. In previous work, we demonstrated that a novel application of attenuated total reflectance--Fourier transform infrared (ATR-FTIR) spectroscopy allows for direct probing of wetting states and dynamics on nanostructured surfaces. Building on these insights, this project will further explore how various structural geometries, pattern densities, surface chemistries, and wet solutions affect the wetting state at the nanoscale. |
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Monthly Plan |
1st Month |
Safety, cleanroom, lab and tool training, literature study |
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2nd Month |
tool training + ATR crystal preparation, literature study |
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3rd Month |
Silane oven deposition, contact angle + ATR-FTIR experiments (L/S structure 1) |
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4th Month |
Silane oven deposition, contact angle + ATR-FTIR experiments (L/S structure 2) |
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5th Month |
Silane oven deposition, contact angle + ATR-FTIR experiments (L/S structure 3) |
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6th Month |
review results and compare with FDTD simulations |
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7th Month |
Silane oven deposition, contact angle + ATR-FTIR experiments (Asymmetric pillar 1) |
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8th Month |
Silane oven deposition, contact angle + ATR-FTIR experiments (Asymmetric pillar 2) |
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9th Month |
review results and compare with FDTD simulations |
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10th Month |
review results and compare with FDTD simulations |
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11th Month |
wetting model development, drafting of paper |
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12th Month |
drafting of paper, report final results in group meeting |